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ICS9LPRS501 1121f?02/23/09 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1 datasheet idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor recommended application: key specifications: ck505 compliant clock with fully integrated voltage regulator and internal series resistor on differential outputs, pcie gen 1 compliant ? cpu outputs cycle-cycle jitter < 85ps src output cycle-cycle jitter < 125ps pci outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on cpu & src clocks tssop pin configuration output features: 2 - cpu differential low power push-pull pairs 10 - src differential low power push-pull pairs 1 - cpu/src selectable differential low power push-pull pair 1 - src/dot selectable differential low power push-pull pair 5 - pci, 33mhz 1 - pci_f, 33mhz free running 1 - usb, 48mhz 1 - ref, 14.318mhz features/benefits: does not require external pass transistor for voltage regulator integrated series resistors on differential outputs, z o =50 ? supports spread spectrum modulation, default is 0.5% down spread uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning one differential push-pull pair selectable between src and two single-ended outputs table 1: cpu frequency select table pci0/cr#_a 1 64 sclk vddpci 2 63 sdata pci1/cr#_b 3 62 ref0/fslc/test_sel pci2/tme 4 61 vddref pci3 5 60 x1 pci4/src5_en 6 59 x2 pci_f5/itp_en 7 58 gndref gndpci 8 57 fslb/test_mode vdd48 9 56 ck_pwrgd/pd# usb_48mhz/fsla 10 55 vddcpu gnd4811 54cput0 vdd96_io 12 53 cpuc0 dott_96/ s rct0 13 52 gndcp u dotc_96/srcc0 14 51 cput1_f gnd 15 50 cpuc1_f vdd 16 49 vddcpu_io srct1/se1 17 48 nc srcc1/se2 18 47 cput2_itp/srct8 gnd 19 46 cpuc2_itp/srcc8 vddpll3_io 20 45 vddsrc_io srct2/satat 21 44 srct7/cr#_f srcc2/satac 22 43 srcc7/cr#_e gndsrc 23 42 gndsrc srct3/cr#_c 24 41 srct6 srcc3/cr#_d 25 40 srcc6 vddsrc_io 26 39 vddsrc srct427 38pci_stop#/srct5 srcc4 28 37 cpu_stop#/srcc5 gndsrc 29 36 vddsrc_io srct9 30 35 srcc10 srcc9 31 34 srct10 srcc11/cr#_g 32 33 srct11/cr#_h 9lprs501 fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 11 1 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. 96.00 reserved 100.00 33.33 14.318 48.00
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 2 tssop pin description pin # pin name type description 1 pci0/cr#_a i/o 3.3v pci clock output or clock request control a for either src0 or src2 pair the power-up default is pci0 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 0 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1= cr#_a controls src2 pair 2 vddpci pwr power supply pin for the pci outputs, 3.3v nominal 3 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for either src1 or src4 pair the power-up default is pci1 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 1 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 6 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1= cr#_b controls src4 pair 4pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) latched input. this pin is sampled on power-up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 5 pci3 out 3.3v pci clock output. 6 pci4/src5_en i/o 3.3v pci clock output / src5 pair or pci_stop#/cpu_stop# enable strap. on powerup, the logic value on this pin determines if the src5 pair is enabled or if cpu_stop#/pci_stop# is enabled (pins 37 and 38). the latched value controls the pin function on pins 37 and 38 as follows 0 = pci_stop#/cpu_stop# 1 = src5/src5# 7 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable strap. this output is not affected by the state of the pci_stop# pin. on powerup, the state of this pin determines whether pins 38 and 39 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 8 gndpci pwr ground for pci clocks. 9 vdd48 pwr power supply for usb clock, nominal 3.3v. 10 usb_48mhz/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 11 gnd48 pwr ground pin for the 48mhz outputs. 12 vdd96_io pwr power supply for dot96 outputs, vdd96_io is 1.05 to 3.3v with +/-5% tolerance 13 dott_96/srct0 out true clock of src or dot96. the power-up default function is src0. after powerup, this pin function may be changed to dot96 via smbus byte 1, bit 7 as follows: 0= src0 1=dot96 14 dotc_96/srcc0 out complement clock of src or dot96. the power-up default function is src0#. after powerup, this pin function may be changed to dot96# via smbus byte 1, bit 7 as follows 0= src0# 1=dot96# 15 gnd pwr ground pin for the dot96 clocks. 16 vdd pwr power supply for src / se1 and se2 clocks, 3.3v nominal.
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 3 tssop pin description (continued) pin # pin name type description 17 srct1/se1 out true clock of differential src1 clock pair / 3.3v single-ended output. the powerup default is 100 mhz src, -0.5% downspread. the pin function may be changed via smbus b1b[4:1] 18 srcc1/se2 out complement clock of differential src1 clock pair / 3.3v single-ended output. the powerup default is 100 mhz src, -0.5% downspread. the pin function may be changed via smbus b1b[4:1] 19 gnd pwr ground pin for src / se1 and se2 clocks, pll3. 20 vddpll3_io pwr power supply for pll3 output. vddpll3_io is 1.05 to 3.3v with +/-5% tolerance 21 srct2/satat out true clock of differential src/sata clock pair. 22 srcc2/satac out complement clock of differential src/sata clock pair. 23 gndsrc pwr ground pin for src clocks. 24 srct3/cr#_c i/o true clock of differential src clock pair/ clock request control c for either src0 or src2 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1= cr#_c controls src2 pair 25 srcc3/cr#_d i/o complementary clock of differential src clock pair/ clock request control d for either src1 or src4 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1= cr#_d controls src4 pair 26 vddsrc_io pwr power supply for src clocks. vddsrc_io is 1.05 to 3.3v with +/-5% tolerance 27 srct4 i/o true clock of differential src clock pair 4 28 srcc4 i/o complement clock of differential src clock pair 4 29 gndsrc pwr ground pin for src clocks. 30 srct9 out true clock of differential src clock pair. 31 srcc9 out complement clock of differential src clock pair. 32 srcc11/cr#_g i/o src11 complement /clock request control for src9 pair the power-up default is src11#, but this pin may also be used as a clock request control of src9 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src9 pair using byte 6, bit 5 of smbus configuration space byte 6, bit 5 0 = src11# enabled (default) 1= cr#_g controls src9
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 4 tssop pin description (continued) pin # pin name type description 33 srct11/cr#_h i/o src11 true or clock request control h for src10 pair the power-up default is src11, but this pin may also be used as a clock request control of src10 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3 bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src10 pair using byte 6, bit 4 of smbus configuration space byte 6, bit 4 0 = src11 enabled (default) 1= cr#_h controls src10. 34 srct10 out true clock of differential src clock pair. 35 srcc10 out cpmplement clock of differential src clock pair. 36 vddsrc_io pwr power supply for src outputs. vddsrc_io is 1.05 to 3.3v with +/-5% tolerance 37 cpu_stop#/srcc5 i/o stops all cpu clocks, except those set to be free running clocks / complement clock of differential src pair. the function of this pin is set up by the power-up strap on pin 6, pci4/src5_en. the logic value sampled on pin 6 at power-up sets the function as follows: 0= cpu_stop# 1 = src5 in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 38 pci_stop#/srct5 i/o stops all pci clocks, except those set to be free r unning clo cks / complement clock of differential src pair. the function of this pin is set up by the power-up strap on pin 6, pci4/src5_en. the logic value sampled on pin 6 at power-up sets the function as follows: 0= pci_stop# 1 = src5# in amt mode, this pin is a clock input which times the fsc, fsb, fsa bits shifted in on pin 37. 39 vddsrc pwr vdd pin for src internal circuits, 3.3v nominal 40 srcc6 out complement clock of low power differential src clock pair. 41 srct6 out true clock of low power differential src clock pair. 42 gndsrc pwr ground for src clocks 43 srcc7/cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may also be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr#_e controls src6. 44 srct7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair using byte 6, bit 6 of smbus configuration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr#_f controls src8. 45 vddsrc_io pwr power supply for src outputs. vddsrc_io is 1.05 to 3.3v with +/-5% tolerance 46 cpuc2_itp/srcc8 out complement clock of low power differential cpu2/complement clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8# 1 = itp# 47 cput2_itp/srct8 out true clock of low power differential cpu2/true clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 48 nc n/a no connect
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 5 tssop pin description (continued) fully integrated regulator connection for desktop/mobile applications pin # pin name type description 49 vddcpu_io pwr supply for cpu outputs. vddcpu_io is 1.05 to 3.3v with +/-5% tolerance 50 cpuc1_f out complement clock of low power differenatial cpu clock pair. this clock will be free-running during iamt. 51 cput1_f out true clock of low power differential cpu clock pair. this clock will be free-r unning during iamt. 52 gndcpu pwr ground pin for cpu outputs 53 cpuc0 out complement clock of low power differential cpu clock pair. 54 cput0 out true clock of low power differential cpu clock pair. 55 vddcpu pwr power supply 3.3v nominal. 56 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 57 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 58 gndref pwr ground pin for crystal osc illator circuit 59 x2 out crystal output, nominally 14.318mhz. 60 x1 in crystal input, nominally 14.318mhz. 61 vddref pwr power pin for the ref outputs, 3.3v nominal. 62 ref0/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values/ test_sel: 3-level latched input to enable test mode. refer to test clarification table. 63 sdata i/o data pin for smbus circuitry, 5v tolerant. 64 sclk in clock pin of smbus circuitry, 5v tolerant. ics9lpr501 ICS9LPRS501 1.05v to 3.3v (+/-5%) nc pin 48 vddcpu_io, pin 49 vddsrc_io pin 45,36,26 vddpll3_io, pin 20 vdd96_io, pin 12 src_io decoupling network pll3_io decoupling network cpu_io decoupling network 96_io decoupling network
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 6 fslb/test_mode ck_pwrgd/pd# vddcpu cput0 cpuc0 gndcpu cput1_f cpuc1_f vddcpu_io nc cput2_itp/srct8 cpuc2_itp/srcc8 vddsrc_io srct7/cr#_f srcc7/cr#_e gndsrc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gndref 1 48 srct6 x2 2 47 srcc6 x1 3 46 vddsrc vddref 4 45 pci_stop#/srct5 ref0/fslc/test_sel 5 44 cpu_stop#/srcc5 sdata 6 43 vddsrc_io sclk 7 42 srcc10 pci0/cr#_a 8 41 srct10 vddpci 9 40 srct11/cr#_h pci1/cr#_b 10 39 srcc11/cr#_g pci2/tme 11 38 srcc9 pci3 12 37 srct9 pci4/src5_en 13 36 gndsrc pci_f5/itp_en 14 35 srcc4 gndpci 15 34 srct4 vdd48 16 33 vddsrc_io 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 usb_48mhz/fsla gnd48 vdd96_io dott_96/srct0 dotc_96/srcc0 gnd vdd srct1/se1 srcc1/se2 gnd vddpll3_io srct2/satat srcc2/satac gndsrc srct3/cr#_c srcc3/cr#_d ICS9LPRS501 mlf pin configuration
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 7 mlf pin description pin # pin name type description 1 gndref pwr ground pin for crystal oscillator circuit 2 x2 out crystal output, nominally 14.318mhz. 3 x1 in crystal input, nominally 14.318mhz. 4 vddref pwr power pin for the ref outputs, 3.3v nominal. 5 ref0/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values/ test_sel: 3-level latched input to enable test mode. refer to test clarification table. 6 sdata i/o data pin for smbus circuitry, 5v tolerant. 7 sclk in clock pin of smbus circuitry, 5v tolerant. 8 pci0/cr#_a i/o 3.3v pci clock output or clock request control a for either src0 or src2 pair the power-up default is pci0 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 0 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1= cr#_a controls src2 pair 9 vddpci pwr power supply pin for the pci outputs, 3.3v nominal 10 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for either src1 or src4 pair the power-up default is pci1 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 1 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 6 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1= cr#_b controls src4 pair 11 pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) latched input. this pin is sampled on power-up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 12 pci3 out 3.3v pci clock output. 13 pci4/src5_en i/o 3.3v pci clock output / src5 pair or pci_stop#/cpu_stop# enable strap. on powerup, the logic value on this pin determines if the src5 pair is enabled or if cpu_stop#/pci_stop# is enabled (pins 29 and 30). the latched value controls the pin function on pins 29 and 30 as follows 0 = pci_stop#/cpu_stop# 1 = src5/src5# 14 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable strap. this output is not affected by the state of the pci_stop# pin. on powerup, the state of this pin determines whether pins 38 and 39 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 15 gndpci pwr ground for pci clocks. 16 vdd48 pwr power supply for usb clock, nominal 3.3v.
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 8 mlf pin description (continued) pin # pin name type description 17 usb_48mhz/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 18 gnd48 pwr ground pin for the 48mhz outputs. 19 vdd96_io pwr power supply for dot96 outputs, vdd96_io is 1.05 to 3.3v with +/-5% tolerance 20 dott_96/srct0 out true clock of src or dot96. the power-up default function is src0. after powerup, this pin function may be changed to dot96 via smbus byte 1, bit 7 as follows: 0= src0 1=dot96 21 dotc_96/srcc0 out complement clock of src or dot96. the power-up default function is src0#. after powerup, this pin function may be changed to dot96# via smbus byte 1, bit 7 as follows 0= src0# 1=dot96# 22 gnd pwr ground pin for the dot96 clocks. 23 vdd pwr power supply for src / se1 and se2 clocks, 3.3v nominal. 24 srct1/se1 out true clock of differential src1 clock pair / 3.3v single-ended output. the powerup default is 100 mhz src, -0.5% downspread. the pin function may be changed via smbus b1b[4:1] 25 srcc1/se2 out complement clock of differential src1 clock pair / 3.3v single-ended output. the powerup default is 100 mhz src, -0.5% downspread. the pin function may be changed via smbus b1b[4:1] 26 gnd pwr ground pin for src / se1 and se2 clocks, pll3. 27 vddpll3_io pwr power supply for pll3 output. vddpll3_io is 1.05 to 3.3v with +/-5% tolerance 28 srct2/satat out true clock of differential src/sata clock pair. 29 srcc2/satac out complement clock of differential src/sata clock pair. 30 gndsrc pwr ground pin for src clocks. 31 srct3/cr#_c i/o true clock of differential src clock pair/ clock request control c for either src0 or src2 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1= cr#_c controls src2 pair 32 srcc3/cr#_d i/o complementary clock of differential src clock pair/ clock request control d for either src1 or src4 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1= cr#_d controls src4 pair
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 9 mlf pin description (continued) pin # pin name type description 33 vddsrc_io pwr power supply for src clocks. vddsrc_io is 1.05 to 3.3v with +/-5% tolerance 34 srct4 i/o true clock of differential src clock pair 4 35 srcc4 i/o complement clock of differential src clock pair 4 36 gndsrc pwr ground pin for src clocks. 37 srct9 out true clock of differential src clock pair. 38 srcc9 out complement clock of differential src clock pair. 39 srcc11/cr#_g i/o src11 complement /clock request control for src9 pair the power-up default is src11#, but this pin may also be used as a clock request control of src9 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src9 pair using byte 6, bit 5 of smbus configuration space byte 6, bit 5 0 = src11# enabled (default) 1= cr#_g controls src9 40 srct11/cr#_h i/o src11 true or clock request control h for src10 pair the power-up default is src11, but this pin may also be used as a clock request control of src10 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 6 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src10 pair using byte 6, bit 4 of smbus configuration space byte 6, bit 4 0 = src11 enabled (default) 1= cr#_h controls src10. 41 srct10 out true clock of differential src clock pair. 42 srcc10 out cpmplement clock of differential src clock pair. 43 vddsrc_io pwr power supply for src outputs. vddsrc_io is 1.05 to 3.3v with +/-5% tolerance 44 cpu_stop#/srcc5 i/o stops all cpu clocks, except those set to be free running clocks / complement clock of differential src pair. the function of this pin is set up by the power-up strap on pin 6, pci4/src5_en. the logic value sampled on pin 6 at power-up sets the function as follows: 0= cpu_stop# 1 = src5 in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 45 pci_stop#/srct5 i/o stops all pci clocks, except those set to be free running clocks / complement clock of differential src pair. the function of this pin is set up by the power-up strap on pin 6, pci4/src5_en. the logic value sampled on pin 6 at power-up sets the function as follows: 0= pci_stop# 1 = src5# in amt mode, this pin is a clock input which times the fsc, fsb, fsa bits shifted in on pin 37. 46 vddsrc pwr vdd pin for src internal circuits, 3.3v nominal 47 srcc6 out complement clock of low power differential src clock pair. 48 srct6 out true clock of low power differential src clock pair.
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 10 mlf pin description (continued) pin # pin name type description 49 gndsrc pwr ground for src clocks 50 srcc7/cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may also be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr#_e controls src6. 51 srct7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair using byte 6, bit 6 of smbus configuration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr#_f controls src8. 52 vddsrc_io pwr power supply for src outputs. vddsrc_io is 1.05 to 3.3v with +/-5% tolerance 53 cpuc2_itp/srcc8 out complement clock of low power differential cpu2/complement clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8# 1 = itp# 54 cput2_itp/srct8 out true clock of low power differential cpu2/true clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 55 nc n/a no connect 56 vddcpu_io pwr supply for cpu outputs. vddcpu_io is 1.05 to 3.3v with +/-5% tolerance 57 cpuc1_f out complement clock of low power differenatial cpu clock pair. this clock will be free-running during iamt. 58 cput1_f out true clock of low power differential cpu clock pair. this clock will be free-running during iamt. 59 gndcpu pwr ground pin for cpu outputs 60 cpuc0 out complement clock of low power differential cpu clock pair. 61 cput0 out true clock of low power differential cpu clock pair. 62 vddcpu pwr power supply 3.3v nominal. 63 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 64 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table.
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 11 funtional block diagram power groups ICS9LPRS501 follows intel ck505 yellow cover specification. this clock synthesizer provides a single chip solution for next generation intel processors and intel chipsets. ICS9LPRS501 is driven with a 14.318mhz crystal. it also provides a tight ppm accuracy output for serial ata and pci-express support. general description ref cpu(1:0) cpu pll1 ss osc ref src(11-9,7:3) pll2 non-ss pll3 ss 7 src8/itp pci src2/sata src1/se(2:1) se outputs sata dot96mhz pci33mhz src src s r c _ m a i n pci33mhz differential output src0/dot96 48mhz 48mhz cpu fsla ckpwrgd/pd# pci_stop# cpu_stop# cr#_(a:h) src5_en itp_en fslc/testsel fslb/testmode control logic x1 x2 vdd gnd 49 52 cpuclk low power outputs 55 52 26, 36, 45 23, 29, 42 low power outputs 39 23, 29, 42 pll 1 20 19 low power outputs 16 19 pll 3 12 11 dot 96mhz low power outputs 911 61 58 28 pin number description pll3/se master clock, analog usb 48 xtal, ref pciclk srcclk
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 12 electrical characteristics - input/supply/common output parameters parameter symbol conditions min max units notes ambient operating temp tambient - 0 70 c 1 supply voltage vddxxx supply voltage 3.135 3.465 v 1 supply voltage vddxxx_io low-voltage differential i/o supply 0.99 3.465 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v ols e single-ended outputs, i ol = 1 ma 0.4 v 1 output high voltage v ohdif differential outputs 0.7 0.9 v 1 output low voltage v oldif differential outputs 0.4 v 1 low threshold input- high voltage (test mode) v ih_fs_test 3.3 v +/-5% 2 v dd + 0.3 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 i dd_default 3.3v supply, pll3 off 200 ma 1 i dd_pll3dif 3.3v supply, pll3 differential out 250 ma 1 i dd_pll3se 3.3v supply, pll3 single-ended out 250 ma 1 i dd_io 0.8v supply, differential io current, all outputs enabled 70 ma 1 i dd_pd3.3 3.3v supply, power down mode 10 ma 1 i dd_pdio 0.8v io supply, power down mode 0.1 ma 1 i dd_iamt3.3 3.3v supply, iamt mode 26 ma 1 i dd_iamt0.8 0.8v io supply, iamtmode 10 ma 1 input frequency f i v dd = 3.3 v 15 mhz 2 pin inductance l p in 7nh1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 6 pf 1 operating supply current power down current iamt mode current input capacitance absolute maximum ratings parameter symbol conditions min max units notes maximum supply voltage vddxxx supply voltage 4.6 v 1,7 maximum supply voltage vddxxx_io low-voltage differential i/o supply 0.99 3.8 v 1,7 maximum input voltage v ih 3.3v lvcmos inputs 4.6 v 1,7,8 minimum input voltage v il any input gnd - 0.5 v 1,7 storage temperature ts - -65 150 c1,7 case temperature tcase - 115 c 1,7 input esd protection esd prot human body model 2000 v 1,7
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 13 ac electrical characteristics - input/common parameters parameter symbol conditions min max units notes clk stabiliz ation t stab from vdd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 tdrive_src t drsrc src output enable after pci_stop# de-assertion 15 ns 1 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns 1 tfall_pd# t fall 5ns1 trise_pd# t rise 5ns1 fall/rise time of pd#, pci_stop# and cpu_stop# inputs ac electrical characteristics - low power differential outputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 2.5 8 v/ns 1,2 falling edge slew rate t flr differential measurement 2.5 8 v/ns 1,2 slew rate variation t slvar single-ended measurement 20 % 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 cpu[1:0] skew cpu skew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpu skew20 differential measurement 150 ps 1 src[10:0] skew src skew differential measurement 3000 ps 1 electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,6 33.33mhz output nominal 30.00900 ns 6 33.33mhz output spread 30.15980 ns 6 absolute min/max period t abs 33.33mhz output nominal/spread 29.49100 30.65980 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t skew v t = 1.5 v 250 ps 1 intentional pci-pci delay t dela y v t = 1.5 v ps 1,9 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 200 nominal clock period 29.99100 t period output high current i oh output low current i ol
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 14 intentional pci clock to clock delay 200 ps nominal steps pci0 pci1 pci2 pci3 pci4 pci_f5 1.0ns electrical characteristics - usb48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 48.00mhz output nominal 20.83125 20.83542 ns 2 absolute min/max period t abs 48.00mhz output nominal 20.48130 21.18540 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 350 ps 1 output high current i oh i ol output low current electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t p eriod 14.318mhz output nominal 69.8203 69.8622 ns 2 absolute min/max period t abs 14.318mhz output nominal 69.8203 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 15 electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ols m b @ i pullup 0.4 v 1 current sinking at v ols m b = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1 notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# falling) 6 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#. the average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 7 operation under these conditions is neither implied, nor guaranteed. 9 see pci clock-to-clock delay figure 8 maximum input voltage is not to exceed maximum vdd electrical characteristics - se1/2=25mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 25.00mhz output nominal 39.99600 40.00400 ns 1 absolute min/max period t abs 25.00mhz output nominal 39.32360 40.67640 ns 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 jitter, long term t ltj v t = 1.5 v @ 10us delay 3000 ps 1 output high current i oh output low current i ol
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 16 fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 00 0266.66 00 1133.33 01 0200.00 01 1166.66 10 0333.33 10 1100.00 11 0400.00 11 1 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. table 1: cpu fre q uenc y select table 96.00 reserved 100.00 33.33 14.318 48.00 pin 17 pin 18 spread mhz mhz % 000 0 0 0 0 1 100.00 100.00 0.5% down spread srcclk1 from src_main 0 0 1 0 100.00 100.00 0.5% down spread only srcclk1 from pll3 0 0 1 1 100.00 100.00 1% down spread only srcclk1 from pll3 0 1 0 0 100.00 100.00 1.5% down spread only srcclk1 from pll3 0 1 0 1 100.00 100.00 2% down spread only srcclk1 from pll3 0 1 1 0 100.00 100.00 2.5% down spread only srcclk1 from pll3 011 1 n/a n/a n/a n/a 1 0 0 0 24.576 24.576 none 24.576mhz on se1 and se2 1 0 0 1 24.576 98.304 none 24.576mhz on se1, 98.304mhz on se2 1 0 1 0 98.304 98.304 none 98.304mhz on se1 and se2 1 0 1 1 27.000 27.000 none 27mhz on se1 and se2 1 1 0 0 25.000 25.000 none 25mhz on se1 and se2 110 1 n/a n/a n/a n/a 111 0 n/a n/a n/a n/a 111 1 n/a n/a n/a n/a comment pll 3 disabled b1b1 b1b4 b1b3 b1b2 table 2: pll3 quick confi g uration
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 17 table 3: io_vout select table b9b2 b9b1 b9b0 io_vout 000 0.3v 001 0.4v 010 0.5v 011 0.6v 100 0.7v 101 0.8v 110 0.9v 111 1.0v table 4: device id table 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0 100 1 101 0 101 1 110 0 110 1 111 0 111 1 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 64 pin tssop/qfn b8b5 b8b4 comment 56 pin tssop/qfn b8b7 b8b6
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 18 pci_stop# power management smbus oe bit pci_stop# stop drive mode stoppable free running stoppable free running 1x running running running running 0 ck= high ck# = low running 1 ck= pull down ck# = low running disable xx cpu_stop# power management smbus oe bit pci_stop# sto p drive mode sto pp able free runnin g 1x running running 0 ck= high ck# = low running 1 ck= pull down ck# = low running disable xx cr# power management smbus oe bit cr# sto p drive mode sto pp able free runnin g 1 running running 0 disable x pd# power management device state w/o latched in p u t w/latched in p u t latches open power down m1 virtual power cycle to latches open single-ended clocks differential clocks (except cpu) low ck = pull down, ck# = low differential clocks differential clocks enable 0 low low enable 0 ck= pull down, ck# = low low enable ck= pull down, ck# = low x ck= pull down, ck# = low low hi-z single-ended clocks ck= pull down ck# = low ck= pull down ck# = low cpu1 ck= pull down, ck# = low ck= pull down, ck# = low ck= pull down, ck# = low running differential clocks (except cpu1) ck= pull down ck# = low
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 19 general smbus serial interface information for the ICS9LPRS501 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the beginning byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controller (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 20 byte 0 fs readback and pll selection register bit pin name description type 0 1 default 7 - fslc cpu freq. sel. bit (most significant) r see table 1 : cpu frequency select table latch 6 - fslb cpu freq. sel. bit r latch 5 - fsla cpu freq. sel. bit (least significant) r latch 4- iamt_en set via smbus or dynamically by ck505 if detects dynamic m1 rw legacy mode iamt enabled 0 3 reserved reserved rw 0 2 - src_main_sel select source for src main rw src main = pll1 src main = pll3 0 1 - sata_sel select source for sata clock rw sata = src_main sata = pll2 0 0 - pd_restore 1 = on power down de-assert return to last known state 0 = clear all smbus configurations as if cold power-on and go to latches open state this bit is ignored and treated at '1' if device is in iamt mode. rw configuration not saved configuration saved 1 byte 1 dot96 select and pll3 quick config register bit pin name description type 0 1 default 7 13/14 src0_sel select src0 or dot96 rw src0 dot96 0 6 - pll1_ssc_sel select 0.5% down or center ssc rw down spread center spread 0 5 pll3_ssc_sel select 0.5% down or center ssc rw down spread center spread 0 4 pll3_cf3 pll3 quick config bit 3 rw 0 3 pll3_cf2 pll3 quick config bit 2 rw 0 2 pll3_cf1 pll3 quick config bit 1 rw 0 1 pll3_cf0 pll3 quick config bit 0 rw 1 0 pci_sel pci_sel rw pci from pll1 pci from src_main 1 byte 2 output enable register bit pin name description type 0 1 default 7ref_oe output enable for ref, if disabled output is tri-stated rw output disabled output enabled 1 6 usb_oe output enable for usb rw output disabled output enabled 1 5 pcif5_oe output enable for pci5 rw output disabled output enabled 1 4 pci4_oe output enable for pci4 rw output disabled output enabled 1 3 pci3_oe output enable for pci3 rw output disabled output enabled 1 2 pci2_oe output enable for pci2 rw output disabled output enabled 1 1 pci1_oe output enable for pci1 rw output disabled output enabled 1 0 pci0_oe output enable for pci0 rw output disabled output enabled 1 byte 3 output enable register bit pin name description type 0 1 default 7 src11_oe output enable for src11 rw output disabled output enabled 1 6 src10_oe output enable for src10 rw output disabled output enabled 1 5 src9_oe output enable for src9 rw output disabled output enabled 1 4 src8/itp_oe output enable for src8 or itp rw output disabled output enabled 1 3 src7_oe output enable for src7 rw output disabled output enabled 1 2 src6_oe output enable for src6 rw output disabled output enabled 1 1 src5_oe output enable for src5 rw output disabled output enabled 1 0 src4_oe output enable for src4 rw output disabled output enabled 1 byte 4 output enable and spread spectrum disable register bit pin name description type 0 1 default 7 src3_oe output enable for src3 rw output disabled output enabled 1 6 sata/src2_oe output enable for sata/src2 rw output disabled output enabled 1 5 src1_oe output enable for src1 rw output disabled output enabled 1 4 src0/dot96_oe output enable for src0/dot96 rw output disabled output enabled 1 3 cpu1_oe output enable for cpu1 rw output disabled output enabled 1 2 cpu0_oe output enable for cpu0 rw output disabled output enabled 1 1 pll1_ssc_on enable pll1's spread modulation rw spread disabled spread enabled 1 0 pll3_ssc_on enable pll3's spread modulation rw spread disabled spread enabled 1 see table 2: pll3 quick configuration only applies if byte 0, bit 2 = 0.
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 21 byte 5 clock request enable/configuration register bit pin name description type 0 1 default 7 cr#_a_en enable cr#_a (clk req), pci0_oe must be = 1 for this bit to take effect rw disable cr#_a enable cr#_a 0 6 cr#_a_sel sets cr#_a to control either src0 or src2 rw cr#_a -> src0 cr#_a -> src2 0 5 cr#_b_en enable cr#_b ( clk re q) rw disable cr#_b enable cr#_b 0 4 cr#_b_sel sets cr#_b -> src1 or src4 rw cr#_b -> src1 cr#_b -> src4 0 3 cr#_c_en enable cr#_c ( clk re q) rw disable cr#_c enable cr#_c 0 2 cr#_c_sel sets cr#_c -> src0 or src2 rw cr#_c -> src0 cr#_c -> src2 0 1 cr#_d_en enable cr#_d ( clk re q) rw disable cr#_d enable cr#_d 0 0 cr#_d_sel sets cr#_d -> src1 or src4 rw cr#_d -> src1 cr#_d -> src4 0 byte 6 clock request enable/configuration and stop control register bit pin name description type 0 1 default 7 cr#_e_en enable cr#_e ( clk re q) -> src6 rw disable cr#_e enable cr#_e 0 6 cr#_f_en enable cr#_f (clk req) -> src8 rw disable cr#_f enable cr#_f 0 5 cr#_g_en enable cr#_g ( clk re q) -> src9 rw disable cr#_g enable cr#_g 0 4 cr#_h_en enable cr#_h (clk req) -> src10 rw disable cr#_h enable cr#_h 0 3 reserved reserved rw 0 2 reserved reserved rw 0 1 sscd_stp_crtl ( src1 ) if set, sscd (src1) stops with pci_stop# rw free running stops with pci_stop# assertion 0 0src_stp_crtl if set, srcs (except src1) stop with pci_stop# rw free running stops with pci_stop# assertion 0 byte 7 vendor id/ revision id bit pin name description type 0 1 default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 byte 8 device id and output enable register bit pin name description type 0 1 default 7 device_id3 r 0 6 device_id2 r 0 5 device_id1 r 0 4 device_id0 r 1 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 se1_oe out p ut enable for se1 rw disabled enabled 0 0se2_oe output enable for se2 rw disabled enabled 0 byte 9 output control register bit pin name description type 0 1 default 7 pcif5 stop en allows control of pcif5 with assertion of pci_stop# rw free running stops with pci_stop# assertion 0 6 tme_readback truested mode enable ( tme ) stra p status r normal o p eration no overclockin g 0 5 reserved reserved rw - - 1 4 test mode select allows test select, i g nores ref/fsc/testsel rw out p uts hi-z out p uts = ref/n 0 3 test mode entry allows entry into test mode, ignores fsb/testmode rw normal operation test mode 0 2 io_vout2 io output voltage select (most significant bit) rw 1 1 io_vout1 io out p ut volta g e select rw 0 0 io_vout0 io output voltage select (least significant bit) rw 1 revision id vendor id ics is 0001, binary table of device identifier codes, used for differentiating between ck505 package options, etc. vendor specific see device id table see table 3: v_io selection (default is 0.8v)
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 22 byte 10 ck505 rev 0.85 functions (ics rev h s ilicon and higher) bit pin name description type 0 1 default 7 src5_en readback readback of src5 enable latch r cpu/pci stop enabled src5 enabled latch 6 reserved rw tbd tbd 0 5 reserved rw tbd tbd 0 4 reserved rw tbd tbd 0 3 reserved rw tbd tbd 0 2 reserved rw tbd tbd 0 1 cpu 1 stop enable enables control of cpu1 with cpu_stop# rw free running stoppable 1 0 cpu 0 stop enable enables control of cpu 0 with cpu_stop# rw free running stoppable 1 byte 11 ck505 rev 1.0 functions (ics rev p silicon and higher) bit pin name description type 0 1 default 7 reserved rw tbd tbd 0 6 reserved rw tbd tbd 0 5 reserved rw tbd tbd 0 4 reserved rw tbd tbd 0 3 cpu2_iamt_en enables cpu2(itp) output in iamt state (m1) rw off in iamt free running in iamt 0 2 cpu1_iamt_en enables cpu1 output in iamt state (m1) rw off in iamt free running in iamt 1 1 pcie-gen2 pcie-gen2 status r non-gen2 pcie gen2 compliant 0 0 cpu2 stop enable enables control of cpu2(itp) with cpu_stop# rw free running stoppable 1 byte 12 byte count register bit pin name description type 0 1 default 7 reserved rw 0 6 reserved rw 0 5bc5 rw 0 4bc4 rw 0 3bc3 rw 1 2bc2 rw 1 1bc1 rw 0 0bc0 rw 1 byte 13 ck505 pll1 m/n programming register bit pin name description type 0 1 default 7 n div8 n divider 8 rw - - x 6 n div9 n divider 9 rw - - x 5 m div5 rw - - x 4 m div4 rw - - x 3 m div3 rw - - x 2 m div2 rw - - x 1 m div1 rw - - x 0 m div0 rw - - x byte 14 ck505 pll1 m/n programming register bit pin name description type 0 1 default 7 n div7 rw - - x 6 n div6 rw - - x 5 n div5 rw - - x 4 n div4 rw - - x 3 n div3 rw - - x 2 n div2 rw - - x 1 n div1 rw - - x 0 n div0 rw - - x byte 15 ck505 pll1 spread spectrum control register bit pin name description type 0 1 default 7 ssp7 rw - - x 6 ssp6 rw - - x 5 ssp5 rw - - x 4 ssp4 rw - - x 3 ssp3 rw - - x 2 ssp2 rw - - x 1 ssp1 rw - - x 0 ssp0 rw - - x the decimal representation of m div (5:0) is equal to reference divider value. default at power up = latch-in or byte 0 rom table. reserved read back byte count register the decimal representation of n div (9:0) is equal to vco divider value. default at power up = latch - in or byte 0 rom table. these spread spectrum bits will program the spread pecentage. contact ics for the correct values. reserved
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 23 byte 16 ck505 pll1 spread spectrum control register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 ssp14 rw - - x 5 ssp13 rw - - x 4 ssp12 rw - - x 3 ssp11 rw - - x 2 ssp10 rw - - x 1 ssp9 rw - - x 0 ssp8 rw - - x byte 17 ck505 pll3 m/n programming register bit pin name description type 0 1 default 7 n div8 n divider 8 rw - - x 6 n div9 n divider 9 rw - - x 5 m div5 rw - - x 4 m div4 rw - - x 3 m div3 rw - - x 2 m div2 rw - - x 1 m div1 rw - - x 0 m div0 rw - - x byte 18 ck505 pll3 m/n programming register bit pin name description type 0 1 default 7 n div7 rw - - x 6 n div6 rw - - x 5 n div5 rw - - x 4 n div4 rw - - x 3 n div3 rw - - x 2 n div2 rw - - x 1 n div1 rw - - x 0 n div0 rw - - x byte 19 ck505 pll3 spread spectrum control register bit pin name description type 0 1 default 7 ssp7 rw - - x 6 ssp6 rw - - x 5 ssp5 rw - - x 4 ssp4 rw - - x 3 ssp3 rw - - x 2 ssp2 rw - - x 1 ssp1 rw - - x 0 ssp0 rw - - x byte 20 ck505 pll3 spread spectrum control register bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 ssp14 rw - - x 5 ssp13 rw - - x 4 ssp12 rw - - x 3 ssp11 rw - - x 2 ssp10 rw - - x 1 ssp9 rw - - x 0 ssp8 rw - - x byte 21 m/n enables bit pin name description type 0 1 default 7 reserved rw 0 6 reserved rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 reserved rw 0 1 m/n enable cpu rw disable enable 0 0 m/n enable src/pci rw disable enable 0 the decimal representation of m div (5:0) is equal to reference divider value. default at power up = latch-in or byte 0 rom table. these spread spectrum bits will program the spread pecentage. contact ics for the correct values. the decimal representation of n div (9:0) is equal to vco divider value. default at power up = latch - in or byte 0 rom table. these spread spectrum bits will program the spread pecentage. contact ics for the correct values. these spread spectrum bits will program the spread pecentage. contact ics for the correct values.
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 24 byte 22 cpu m/n programming bit pin na me de scription type 01default 7 n div bit 8 pll 1 m/n programming rw -- x 6 n div bit 9 (intel pll1 cpu) rw -- x 5m div bit 5 rw -- x 4m div bit 4 rw -- x 3m div bit 3 rw -- x 2m div bit 2 rw -- x 1m div bit 1 rw -- x 0m div bit 0 rw -- x byte 23 cpu m/n programming bit pin na me de scription type 01default 7 n div bit 7 pll 1 m/n programming rw -- x 6 n div bit 6 (intel pll1 cpu) rw -- x 5 n div bit 5 rw -- x 4 n div bit 4 rw -- x 3 n div bit 3 rw -- x 2 n div bit 2 rw -- x 1 n div bit 1 rw -- x 0n div bit 0 rw -- x bytes 24-62 reserved byte 63 special power management features (rev p silicon and higher) bit pin na me de scription rw 0 1 de fault 7 reserved rw 0 6 reserved rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 reserved rw 0 1 sata pll power management feature rw off on note 0 xtal pd control controls xtal on/off in legacy pd rw off on 1 note: default is "off" for rev p silicon and higher. *accessing any smbus bytes not shown in the datasheet could result in incorrect clock functions.
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 25 test clarification table comments fslc/ test_sel hw pin fslb/ test_mode hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n b9b3: 1= enter test mode, default = 0 (normal operation) b9b4: 1= ref/n, default = 0 (hi-z) h w sw power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode fslc./test_sel -->3-level latched input if power-up w/ v>2.0v then use test_sel if power-up w/ v<2.0v then use fslc fslb/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 during power-up, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 26 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information 9lprs501 y glft example: designation for tape and reel packaging lead free, rohs compliant (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) xxxx y g lf t min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 64 16.90 17.10 .665 .673 10-0039 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153
idt tm /ics tm 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 1121f?02/23/09 advance information ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor 27 ordering information 9lprs501 y klft example: designation for tape and reel packaging lead free, rohs compliant (optional) package type k = mlf revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) xxxx y k lf t e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e dimensions option 1 dimensions (mm) option 2 dimensions (mm) symbol min. max. symbol min. max. a 0.8 1.0 a 0.8 1.0 n 64 a1 0 0.05 a1 0 0.05 n d 16 a3 a3 n e 16 b 0.18 0.3 b 0.18 0.3 ee d x e basic d x e basic d2 min. / max. 7. 00 7.25 d2 min. / max. 6.00 6.25 e2 min. / max. 7. 00 7.25 e2 min. / max. 6.00 6.25 l min. / max. 0. 30 0.50 l min. / max. 0.30 0.50 0.25 reference 0.50 basic 9.00 x 9.00 0.25 ref erence 0.50 basic 9.00 x 9.00 thermally enhanced, ve ry thin, fine pitch quad flat / no lead plastic package symbol 64l
28 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm ICS9LPRS501 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor this product is protected by united states patent no. 7,342,420 and other patents. rev. issue date description page # a 2/15/2008 1. updated pll3 configuration table. 2. release to final. - b 4/25/2008 updated note on b y te 63. 24 c 9/3/2008 1. updated electrical table. 2. udpated smbus byte 9. 12, 21 d 9/30/2008 added case temperature 12 e 11/12/2008 added electrical table for se1/2=25mhz. 15 f 2/23/2009 updated note under byte 63 table. 24 revision history

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